Some embodiments described herein relate generally to clock gating. More particularly, some embodiments described herein relate to systems and methods for dynamic coarse clock gating packet-processor-engines for power saving in application specific integrated circuits (ASICs) using sliding timing windows to limit current surge.
Clock gating can be used to “turn off”, deactivate, or power down parts of a circuit to reduce the power consumption of a device. A clock signal passes through a logic circuit that can selectively block, or gate, the clock signal. When the clock signal is blocked, logic driven by the gated clock signal suspends operation and does not consume any dynamic power (e.g., power consumed by a processor for a clocked flip-flop). The amount of power savings is related to the amount of logic that is effectively turned off. For example, higher gating on the clock tree (i.e., the clock distribution network) can result in turning off a relatively larger portion of the clock network, thereby using a relatively lower amount of power than would otherwise be used. If the clock is gated at the flip-flop level (for example, immediately before the clock input to a register), very little power is saved because nearly the entire clock network still toggles (e.g., turns on and off).
ASICs includes general circuits, such as logic, memory, and input/output (“I/O”) ports, and a specialized function circuit to implement a function that the general circuits cannot or does not perform. For instance, the specialized function circuit might implement analog or mixed analog/digital circuitry, whereas the circuits might be limited to only digital circuits. In other cases, the specialized function circuit can implement a Peripheral Component Interconnect Express (“PCIe”) physical layer (“PHY”), or any other complex, highly dense circuit.
An ASIC can include a two-dimensional array (fabric) of many relatively small logic elements (referred to herein as power processor elements or PPEs). The basic circuitry of these PPEs is typically the same or substantially the same, and is provided by a subset of the masks that are used to make the ASIC. Accordingly, the masks in this subset can be typically the same or substantially the same. The overall function(s) performed by a PPE can be customized to some extent by customizing one or more additional masks used to make a particular ASIC product (e.g., a structured ASIC). Similarly, connections to, from, and/or between PPEs can be customized by customizing additional masks used to make the product. Because the ASIC typically has the same basic circuitry, the task of designing the ASIC to perform particular tasks is greatly simplified, with increased speed of manufacture, increased reliability, and reduced cost. An entire ASIC does not have to be designed “from scratch.” Instead, only the customizable masks are designed.
A possible use of ASIC technology is to produce ASICs that are functionally equivalent to programmed field-programmable gate arrays (“FPGAs”). After a logic design has been adequately “proven” in an FPGA, the design may be “migrated” to an ASIC. In ASICs, the disposition (location or arrangement) of circuit functions (e.g., logic functions) on the ASIC can be quite different from the disposition of those functions on the FPGA to which the ASIC is supposed to be functionally equivalent. Thus, it may not be possible to simply duplicate on the ASIC the architecture of the related FPGA circuitry for routing, gating, or distributing clock signals to the functional circuitry. Accordingly, it is difficult to transport the efficacy of the FPGA clock gating circuitry to the ASIC.
In some instances, a method for clock gating PPEs of an ASIC includes monitoring the rate and trend (e.g., increasing or decreasing) of traffic (i.e., workload) experienced at or on an interface. In such instances, the ASIC can include a clock gating method based on the rate and trend of the traffic experienced by the entire ASIC, thereby saving a measure of power. Because the clock gating is based on the rate of traffic of the entire ASIC, however, in some instances, one or more PPEs can remain powered on even though they are not immediately needed, thereby requiring power. In addition, frequent clock gating of PPEs in close proximity within the ASIC can result in electrical current surges. Such current surges can result in resonance and failure of the ASIC and/or power supplies.
Thus, a need exists for improved systems and methods of dynamic coarse-clock-gating packet-processor-engines for power saving in ASICs while limiting current surges.